The requirements for cleanliness and the elimination of contaminants in the processing of semiconductor wafers are well documented; see, for example U.S. Pat. Nos. 3,951,541, 3,962,391, 4,093,201, 4,203,940, 4,761,134, 4,978,567, 4,987,016, and Japanese Patent Publication JP 50-90184. To maintain extremely high purity during processing, it is known that such fixtures should be totally free of contaminants, to the extent commercially feasible. It is also known that the carriers should be stable at elevated temperatures, and when subjected to corrosive or oxidizing conditions. Typical Corrosive or oxidizing conditions to which the carriers should remain inert are set forth in U.S. Pat. Nos. 4,987,016 and 4,761,134.
Quartz has been and continues to be the most common material used for these components and fixtures. However, quartz has certain deficiencies, such as structural weakness at high temperatures, susceptibility to etching by commonly used acids, and a coefficient of thermal expansion that differs from that of certain materials which are deposited thereon during normal use.
The prior art discussed below addresses the construction of silicon carbide (SIC) boats which have thus far had the most commercial success--a porous SiC formed by casting. These references disclose the drawbacks of quartz, and the benefits of using SiC. They also disclose the drawbacks of the casting method of producing SiC boats. In order to avoid the deficiencies of porous SiC, prior art methods apply a SiC coating layer by chemical vapor deposition (CVD) over the cast SiC. However, an overcoat of CVD SiC does not completely eliminate the problems with porous SiC, since the coating can crack or chip, and thereby expose the porous SiC. Thus, a carrier that consists entirely of CVD SiC is preferred, thus avoiding the problems of porous SiC.
A number of attempts have been made to improve on quartz. The most successful is a porous silicon carbide infiltrated with silicon, disclosed in U.S. Pat. No. 3,951,587. The problem with such a carrier is that the silicon can etch out when exposed to commonly used cleaning solutions, e.g., strong acids, such as nitric acid, illustrated in U.S. Pat. No. 4,761,134. Other workers (see U.S. Pat. No. 4,761,134) propose to solve this problem by applying an impervious coating, generally a chemical vapor deposited silicon carbide (CVD SiC) coating on the surface of the silicon-filled silicon carbide, or on a porous silicon carbide that has not been filled with silicon (see U.S. Pat. No. 4,987,016). The drawback to these approaches is that any chip, break or crack in the coating will expose the undesirable substrate. U.S. Pat. No. 4,761,134 discusses this drawback as it pertains to CVD SiC applied on an unfilled porous SiC substrate. However, the discussion neglects to point out that a similar weakness is inherent in the approach disclosed and claimed in this reference. U.S. Pat. No. 5,283,089 discloses depositing silicon carbide or silicon nitride onto a silicon carbide or silicon nitride matrix to form wafer boats and other components for semiconductor diffusion furnaces.
The preferred approach is to fabricate the carrier entirely from CVD SiC. In this approach, there is no possibility of a silicon-filled or porous substrate being exposed. The CVD SiC fixture also has the advantage of being cleaner than the cast and sintered, or reaction-bonded SiC carders disclosed in the previously cited references.
The following references describe carriers that are composed entirely of SiC. U.S. Pat. No. 4,978,567 describes a CVD SiC fixture for processing a single wafer at a time, in a furnace designed to do single wafer processing. There is a strong need for a boat for batch processing, capable of holding from 25 to 50 or more wafers. The carrier described and claimed in U.S. Pat. No. 4,978,567 cannot be used for batch processing.
Japanese Patent Application No. JP 50-90184 describes a hollow beam made of CVD SiC to hold wafers. However, this device requires that three or four such beams be joined together by a means of support at the ends. While the boat described in JP 50-90184 fulfills the need for a boat that can hold a plurality of wafers during semiconductor processing, the boat is fragile and relatively complex, and hence costly to manufacture. There is a need for a carrier that uses a single piece of SiC to achieve the same result, and thus is stronger and more economical.
Japanese Patent Application No. Sho 55-82427 discloses a boat consisting of a single piece of silicon carbide, formed by CVD on a graphite substrate. However, the the boat has a rectangular cross-section, which is undesirable because it requires an inefficient use of furnace space. Moreover, the rectangular design causes the mass of the boat to be unnecessarily large, which adds excess thermal inertia, and distorts the thermal pattern developed in the wafers during processing. In diffusion processes, for example, the excess thermal mass of a boat can cause temperature variations across the wafer arena, and thereby alter diffusion patterns. Such variations cannot be offset by changes in process parameters. Still further, excess wafer area is covered by the slot walls or the connecting end members. In addition, the design includes partially enclosed areas that will distort gas flow patterns, and will increase the time required to exhaust gases contained in such partially enclosed areas.
JP 55-82427 also fails to reveal the size of the boat, relative to the size of the wafers to be carried. If the height of the boat is small relative to the wafers, the slots will not provide adequate horizontal support to maintain the wafers in a vertical position. If the height of the boat is large relative to the diameter of the wafers, adequate horizontal support will be provided, but the walls of the slots will then cover an excessive area of each wafer.
U.S. Pat. Nos. 3,962,391, 4,093,201 and 4,203,940 (all assigned to Siemens) describe methods for making carriers which hold a number of wafers and are produced by depositing CVD silicon or CVD silicon carbide on a generally cylindrical graphite form. However, these patents describe carriers that are not suitable for the most widely used wafer processes. The devices described in U.S. Pat. Nos. 3,962,391 and 4,093,201 do not have means for holding the wafers apart, with a uniform gap between each of the wafers which is required in most batch semiconductor processes. U.S. Pat. No. 4,203,940 describes a carrier design that requires the grinding of slots in a silicon or silicon carbide form to provide means for holding the wafers apart with a gap between each pair of wafers. However, the design described in the latter patent allows only two narrow slots to hold each wafer.
Since two slots do not provide adequate wafer support, the industry has developed carriers having four support points to hold each wafer. This is beneficial in the processing of silicon wafers, since it allows the wafers to be held in a more uniform and more parallel position, while minimizing the wafer area covered by the support points. Minimizing the wafer area covered by the support points of the holder maximizes the area of the wafer available for productive use. The general guidelines for the design of these widely used wafer carders is described in the SEMI International Standards, published by Semiconductor Equipment and Materials International, Mountain View, Calif. The information contained in these standards is incorporated herein by reference.